library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
	
entity isequ is
	port (		
		A, B: IN STD_LOGIC_VECTOR (31 downto 0);
		equ: OUT STD_LOGIC
	);		
end isequ;


architecture isequ_arch of isequ is	
begin
	equ <= '1' when A=B else '0';   
end isequ_arch;